1. Field of the Invention
The present invention relates to a high-performance carry lookahead adder (CLA) using an NMOS logic circuit.
2. Description of the Related Art
A microprocessor unit (MPU) is the core component used in personal computers, workstations, and various controller boards, and controls the function of a system by performing software. The core executing component of the MPU or microcontroller unit (MCU) is an arithmetic logic unit (ALU) for executing arithmetic operations, and the representative functional device of the ALU is an adder. Accordingly, implementation of a high-speed adder forms the basis of the construction of a high-speed MPU. The present invention is also applied to custom semiconductor integrated circuits having the MCU or ALU function.
First, the construction of a typical adder is explained. A half adder for performing a binary addition of data a and data b is illustrated in FIG. 1, whose functions are represented as S(sum)=a.sym.b, C (carry)=a.multidot.b (Hereinafter, the added sum is referred to as "S", and the carry is referred to as "C".). FIG. 2 illustrates the construction of a full adder which can execute operations of carry inputs, and whose functions are represented as if P(i)=a(i).sym.b(i), G(i)=a(i).multidot.b(i), then S(i)=P(i).sym.C(i), and C(i+l)=G(i)+P(i).multidot.C(i).
FIG. 3 illustrates the construction of a 4-bit full adder which is composed of 4 full adder blocks. If the delay of a full adder is .DELTA., S(1), S(2), S(3), and S(4) have the delays of 1.DELTA., 2.DELTA., 3.DELTA., and 4.DELTA., respectively, resulting in that C(5) has the delay of 4.DELTA.. Accordingly, if a 32-bit adder is constructed using the above full adders, it has the delay of 32.DELTA., and this causes the implementation of a high-speed adder to be impossible.
In order to solve this problem, a carry lookahead type adder has been developed, whereby an exclusive-OR value P(i) and a logic product value G(i) are produced from 3-bit data a3:0! and b3:0!, and then the sum S(i) and the carry C(i) are produced by logically combining P(i) and G(i). The carry C(i) is given as: EQU C(2)=G(1)+P(1).multidot.C(1) EQU C(3)=G(2)+P(2).multidot.C(2)=G(2)+P(2).multidot.G(1)+P(2).multidot.P(1).mul tidot.C(1) EQU C(4)=G(3)+P(3).multidot.G(2)+P(3).multidot.P(2).multidot.G(1)+P(3).multidot .P(2).multidot.P(1).multidot.C(1) EQU C(5)=G(4)+P(4).multidot.G(3)+P(4).multidot.P(3).multidot.G(2)+P(4).multidot .P(3).multidot.P(2).multidot.G(1) +P(4).multidot.P(3).multidot.P(2).multidot.P(1).multidot.C(1).
The above equations can be effected by a logic circuit of FIG. 4. Referring to the circuit of FIG. 4, the 4-bit full adder, which accompanied the delay of 4.DELTA., has been improved into a circuit capable of obtaining the same result through several logics.
However, the conventional logic circuit has the disadvantage that a carry generator used therein is constructed by CMOS logics using basic gates, and thus it produces a large amount of delay. As a result, the conventional logic circuit has a speed faster than that of the full adder, but it is still unsuitable for achieving a high-speed operation of several hundred MHz.